REDUCTION OF POWER-CONSUMPTION DURING TEST APPLICATION BY TEST VECTORORDERING

Authors
GIRARD P LANDRAULT G PRAVOSSOUDOVITCH S SEVERAC D
Citation
P. Girard et al., REDUCTION OF POWER-CONSUMPTION DURING TEST APPLICATION BY TEST VECTORORDERING, Electronics Letters, 33(21), 1997, pp. 1752-1754
Citations number
3
Categorie Soggetti
Engineering, Eletrical & Electronic
Journal title
Electronics Letters → ACNP
ISSN journal
00135194
Volume
33
Issue
21
Year of publication
1997
Pages
1752 - 1754
Database
ISI
SICI code
0013-5194(1997)33:21<1752:ROPDTA>2.0.ZU;2-F
Abstract
The authors address the problem of testing VLSI circuits without excee ding their power ratings during testing. The proposed approach is base d on re-ordering test vectors in a test sequence to minimise the switc hing activity of the circuit during test application. Results of exper iments are presented which show a power reduction in the range 7.5-55. 8% during test application.