MULTILEVEL FACTORIZATION TECHNIQUE FOR PASS TRANSISTOR LOGIC

There is discussion of a technique of using multi-level logic synthesi s to design pass transistor logic (PTL) based on algebraic factorisati on. Techniques already applied to conventional AND-OR type networks ar e shown to be not useful for factorisation of PTL networks. Starting w ith the set of all prime pass implicants, the steps of selecting a cov er and factorising a function, using a greedy heuristic, are combined. From many examples using MCNC benchmark circuits, the algorithm achie ves a considerable improvement (an average of 14% and up to 50% saving s) over PTL circuits obtained from conventional two-level design metho ds.