DESIGN AND PERFORMANCE OF A LOW-NOISE, LOW-POWER CONSUMPTION CMOS CHARGE AMPLIFIER FOR CAPACITIVE DETECTORS

In this paper, a new design of low noise, low-power consumption charge amplifier is described. Theoretical results show that a total output noise voltage reduction of 0.264 mV has been obtained. This value corr esponds to a 46% reduction compared to the noise performance of a conv entional charge amplifier. A complete readout system including the pro posed charge amplifier has been realized in a 0.8-mu m semiconductor o n insulator (SOI) bipolar complementary metal-oxide-semiconductor (BIC MOS) process. A measured noise performance of 450 electrons at O pF wi th a slope of 44 electrons/pF for a shaping time of 45 ns, a conversio n gain of 20 mV/fC and 1-mW power consumption have been obtained.