A DIGITAL ADAPTIVE BEAMFORMING QAM DEMODULATOR IC FOR HIGH BIT-RATE WIRELESS COMMUNICATIONS

A very large scale integration (VLSI) implementation of an integrated adaptive beamforming processor and quadrature amplitude modulation (QA M) demodulator which will be incorporated into a frequency-hopped spre ad spectrum portable receiver for 2.4-GHz industrial, scientific, and medical (ISM) band applications is presented. The chip performs cohere nt QAM demodulation of variable constellation size and complete adapti ve beamforming processing including four-channel adaptive beamforming combining, a fully programmable training processor, a readable/writabl e system control processor, an acquisition state machine, and a microc ontroller interface. Interleaving area intensive blocks such as the 49 -tap square-root Nyquist Biters and 12 x 12 b multipliers is employed to reduce chip area. This chip can operate as a stand-alone adaptive b eamforming QAM demodulator, or it can work together with an adaptive e qualizer for high bit rate indoor wireless applications. The core area of the chip is 6.22 mm x 4.58 mm in 0.8-mu m CMOS technology, and the power dissipation is 610 mW at 5 V and a 5 MBaud symbol rate. In a 2. 2-dB signal-to-interference-and-noise ratio environment, the receiver chip achieves a link quality of 32.6 dB SNR by performing digital adap tive beamforming to null out interferers.