LOW-POWER VITERBI DECODER FOR CDMA MOBILE TERMINALS

An efficient state-sequential very large scale integration (VLSI) arch itecture and low-power design methodologies ranging from the system-le vel to the layout-level are presented for a large-constraint-length Vi terbi decoder for code division multiple access (CDMA) digital cellula r/personal communication services (PCS) applications. The low-power de sign approaches are also applicable to many other systems and algorith ms. VLSI implementation issues and prototype fabrication results for a state-sequential Viterbi decoder for convolutional codes of rate 1/2 and constraint-length 9 are also described. The chip's core, consistin g of approximately 65 k transistors, occupies 1.9 mm by 3.4 mm in a 0. 8-mu m triple-layer-metal n-well CMOS technology. The chip's measured total power dissipation is 0.24 mW at a 14.4 kb/s data-rate with 0.921 6 MHz clocking at a supply voltage of 1.65 V. The Viterbi decoder pres ented here is the lowest power and smallest area core in its class, to the best of our knowledge.