4-PHASE IMPROVED ADIABATIC PSEUDO-DOMINO LOGIC

A four-phase improved adiabatic pseudo-domino logic family is presente d. The proposed logic family, IAPDL-4 phi, is an extension of IAPDL (i mproved adiabatic pseudo-domino logic). It has the same circuit struct ure as IAPDL, but a different clocking system is applied. A four-phase clock-supply to facilitate pipelining of the design is used in additi on to a reduced pulsewidth for the auxiliary clocks. As a result, the speed is improved by about a factor of two, and power dissipation is d ecreased by similar to 65% for various shift registers at 200 MHz, com pared to IAPDL.