MINIMIZING THE COMPLEXITY OF SRT TABLES

This paper presents an analysis of the complexity of quotient-digit se lection tables in SRT division implementations. SRT dividers are widel y used in VLSI systems to compute floating-point quotients, These divi ders use a fixed number of partial remainder and divisor bits to consu lt a table to select the next quotient-digit in each iteration, This a nalysis derives the allowable divisor and partial remainder truncation s for radix 2 through radix 32, and it quantifies the relationship bet ween table parameters and the complexity of the tables, Several techni ques are presented for further minimizing table complexity, By mapping the tables to a library of standard-cells, delay and area values were measured and are presented for table configurations through radix 32, Several conclusions are drawn based on this data which impacts optimi zed SRT divider designs.