A PERFORMANCE STUDY OF CACHE COHERENCE PROTOCOLS AND WRITE COACHES FOR PARALLEL-MULTITHREADED SHARED-MEMORY MULTIPROCESSORS

According to published research results, no directory-based cache cohe rence protocol provides best performance for all application programs in conventional multiprocessor systems that use sequential consistency models. However, recently it has been claimed that competitive-update protocols are superior to other protocols under a relaxed consistency model. Moreover, incorporating write caches improves the system perfo rmance of clean and competitive-update protocols. In this paper, we ex amine the different effects that occur when processing elements are re placed by parallel-multithreaded processors. According to our simulati on results, the clean protocol provided the best performance for five out of six SPLASH programs. After augmentation with write caches, the clean protocol outperformed others for all applications. Though compet itive-update protocols have been improved, their performance is not be tter than that of write-invalidate protocols for most programs.