PARALLEL CALIBRATED EMULATION AS A TECHNIQUE FOR EVALUATING PARALLEL ARCHITECTURES

We describe the use of a calibrated emulator to simulate a parallel co mputer architecture. The emulator has a virtual clock, but unlike the virtual clock of a simulator, the emulator clock is bound to a fixed f raction of real time. Individual processors time actions independently , thus without the need for a globally synchronised clock value. Each component of the emulator is calibrated (by slowing it down artificial ly) so that the balance of the speeds of all components reflects the b alance of the system under consideration. Unlike an ordinary simulator , a calibrated emulator is inherently parallel. The technique has been applied in the form of a parallel transputer-based emulator developed to evaluate the DDM - a scalable virtual shared memory architecture. The emulator provides performance results of a hardware implementation of the DDM using a calibrated virtual clock. A large transputer platf orm is used to run experiments. A couple of hours are sufficient to em ulate the execution of a realistic application on a large DDM.