TRANSISTOR OPERATION OF 30-NM GATE-LENGTH EJ-MOSFETS

Citation
H. Kawaura et al., TRANSISTOR OPERATION OF 30-NM GATE-LENGTH EJ-MOSFETS, IEEE electron device letters, 19(3), 1998, pp. 74-76
Citations number
4
Categorie Soggetti
Engineering, Eletrical & Electronic
ISSN journal
07413106
Volume
19
Issue
3
Year of publication
1998
Pages
74 - 76
Database
ISI
SICI code
0741-3106(1998)19:3<74:TOO3GE>2.0.ZU;2-E
Abstract
We have fabricated electrically variable shallow junction metal-oxide- silicon field-effect transistors (EJ-MOSFET's) to investigate transist or characteristics of ultrafine-gate MOSFET's. By using EB direct writ ing onto an ultrahigh-resolution negative resist (calixarene), we achi eved a gate length of 32 nm for the first time. The short-channel effe cts were effectively suppressed by electrically induced ultrashallow s ource/drain regions, and the fabricated device exhibited normal transi stor characteristics even in the 32-nm gate-length regime at room temp erature: an ON/OFF current ratio of 10(5) and a cut-off current of 20 pA/mu m.