A HIGH-PERFORMANCE MULTICAST SWITCH AND ITS FEASIBILITY STUDY

This paper describes the design and evaluation of a high-performance m ulticast ATM switch and its feasibility study, including its 40 Gbit/s LSI packaging. The multicast switch is constructed using a serial com bination of rerouting networks and employs an adapted Boolean interval -splitting scheme for a generalized self-routing algorithm. Analysis a nd computer simulation results show that the cell loss probability is easily controlled by increasing the number of switching stages. It is shown that the su itch configuration can be transformed into other pat terns to be built from banyan-based subnetworks of arbitrary size for LSI packaging. It is also shown that an LSI chip integrating an 8 x 8 banyan-based subnetwork using 0.25-mu m CMOS/SIMOX technology can atta in a 40-Gbit/s switching capability.