A CLOCK DISTRIBUTION TECHNIQUE WITH AN AUTOMATIC SKEW COMPENSATION CIRCUIT

This paper describes a low-skew clock distribution technique for multi ple targets. An automatic skew compensation circuit, that detects the round-trip delay through a pair of matched interconnection lines and c orrects the delay of the variable delay lines, maintains clock skew an d delay from among multiple targets below the resolution time of the v ariable delay lines without any manual adjustment. Measured results sh ow that the initial clock skew of 900 ps is automatically reduced to 3 0 ps at a clock frequency of up to 250 MHz with 60 ps of clock jitter. Moreover, they show that the initial clock delay of 1500 ps is cancel led and 60 ps of clock delay can be achieved. The power dissipation is 100 mW at 250 MHz.