PIN ASSIGNMENT FOR MULTI-FPGA SYSTEMS

Multi-FPGA systems have tremendous potential, providing a high-perform ance computing substrate for many different applications, One of the k egs to achieving this potential is a complete, automatic mapping solut ion that creates high-quality mappings in the shortest possible time, In this paper, we consider one step in this process, the assignment of inter-FPGA signals to specific I/O pins on the FPGA's in a multi-FPGA system, We show that this problem can neither be handled by pin assig nment methods developed for other applications nor standard routing al gorithms, Although current mapping systems ignore this issue,,ve show that an intelligent pin assignment method can achieve both quality and mapping speed improvements over random approaches, Intelligent pin as signment methods already exist for multi-FPGA systems, but are restric ted to topologies where logic-bearing FPGA's cannot be directly connec ted. In this paper, we pro,ide three new algorithms for the pin assign ment of multi-FPGA systems with arbitrary topologies, We compare these approaches on several mappings to current multi-FPGA systems, and sho w that the force-directed approach produces better mappings, in signif icantly shorter time, than any of the other approaches.