NEW FAULT MODELS AND EFFICIENT BIST ALGORITHMS FOR DUAL-PORT MEMORIES

The testability problem of dual-port memories is investigated, A funct ional model is defined, and architectural modifications to enhance the testability of such chips are described, These modifications allow mu ltiple access of memory cells for increased test speed with minimal ov erhead on both silicon area and device performance, New fault models a re proposed, and efficient O(root n) test algorithms are described for both the memory array and the address decoders, The new fault models account for the simultaneous dual-access property of the device, In ad dition to the classical static neighborhood pattern-sensitive faults, the array test algorithm covers a new class of pattern sensitive fault s, duplex dynamic neighborhood pattern-sensitive faults (DDNPSF).