Thin film silicon-on-insulator (SOI) devices have an advantage of exce
llent isolation due to the buried oxide layer leading to reduced capac
itance coupling and no latchup in complementary metal-oxide-silicon ci
rcuits compared with bulk silicon devices. Reduced junction area shoul
d lead to lower leakage for a given device. However, because of the bu
ried oxide, stress is built up in the isolation processes, especially
near the island edges, inducing new kinds of leakage currents, which a
re not observed in bulk silicon devices. This letter proposes five lea
kage current models of the partially depleted SOI devices, identifies
their origins, and suggests methods to prevent each type. (C) 1998 Ame
rican Institute of Physics. [S0003-6951(98)01510-0].