2.6 KV 4H-SIC LATERAL DMOSFETS

A 4H-SiC lateral double-implanted metal-oxide-semiconductor (LDMOS) fi eld effect transistor is fabricated in a lightly doped n-epilayer on a n insulating 4H-SiC substrate, After depleting through the epilayer, t he depletion region continues to move laterally toward the drain, The result is an increase in blocking voltage compared to a vertical DMOSF ET fabricated in the same epilayer on a conducting substrate, A blocki ng voltage of 2.6 kV is obtained. nearly double the highest previously demonstrated blocking voltage for a SIC MOSFET.