ACTIVITY MEASURES FOR FAST RELATIVE POWER ESTIMATION IN NUMERICAL TRANSFORMATION FOR LOW-POWER DSP SYNTHESIS

In this paper, we propose a method for power optimization of digital s ignal processing (DSP) systems through reduction of circuit switching activity estimated from high levels in the synthesis hierarchy, namely at numerical and algorithmic levels. The optimization involves applic ation of a numerical transformation called number-splitting on the sys tem characteristic coefficients. The transformation alters the system characteristic coefficients while preserving the input/output relation s. For each set of candidate coefficients, the corresponding signal fl ow-graph is constructed for evaluation of power consumption. First, th e switching activity at all computation nodes of the graph are estimat ed using our novel activity transformation models, which quickly estim ate the activity at the output of the adders and multipliers based on the activity at the inputs. Next, the activity at the inputs of each c omputation node are used to compute the average power consumption by t hat node, using our heuristic power estimators. The optimization frame work can be applied to hardware-dedicated bit-serial, nibble-serial, a s well as programmable word-parallel architectures. We focus on hardwa re-dedicated bit-serial systems and show that up to 35 percent savings in power is achievable.