ARCHITECTURE AND DESIGN OF 1-D ENHANCED CELLULAR NEURAL-NETWORK PROCESSORS FOR SIGNAL-DETECTION

One-dimensional cellular array processor architecture and design for n eural-based partial response (PR) signal detection are presented. Anal og parallel computing approaches have many attractive advantages in ac hieving low power, low cost, and faster processing speed by its unique ly coupled parallel and distributed processing nature. In this paper, we describe the maximum likelihood sequence estimation (MLSE) algorith m for PR signals, the enhanced Cellular Neural Network (CNN) processor array architecture to realize the detection algorithm, and system per formance evaluation. Analytical models and simulations on a design exa mple of the detector have been employed to demonstrate the advantages of this scalable VLSI architecture. A processing rate of 265 Mbps was achieved for a prototype detector on a silicon area of 5.14 mm by 5.81 mm is a 1.2 mu m CMOS technology. The processing rate can be beyond 1 Gbps if it is implemented in the same amount of silicon area by using 0.5 mu m CMOS technology. Such promising results clearly demonstrate t he ability to meet the needs in future high speed data communication b y VLSI realization of maximum likelihood sequence detectors based on t he enhanced cellular neural network paradigm.