USE LOGIC-ANALYZER SETUP HOLD TRIGGERING TO ENSURE TIMING MARGINS/

Authors
SHEPARD CL
Citation
Cl. Shepard, USE LOGIC-ANALYZER SETUP HOLD TRIGGERING TO ENSURE TIMING MARGINS/, EDN, 43(7), 1998, pp. 139
Citations number
NO
Categorie Soggetti
Engineering, Eletrical & Electronic
Journal title
EDN → ACNP
ISSN journal
00127515
Volume
43
Issue
7
Year of publication
1998
Database
ISI
SICI code
0012-7515(1998)43:7<139:ULSHTT>2.0.ZU;2-4
Abstract
With a logic analyzer that offers setup/hold triggering, you can easil y measure system timing margins. Straightforward examples explain how to do it.