ANALYSIS OF LARGE ATM SWITCHES USING A PLATFORM-INDEPENDENT SIMULATION ENVIRONMENT

This paper presents a general simulation approach applied to the probl em of performance evaluation of large switching fabrics. Experimental results in the form of cell queuing delay and buffer occupancy distrib utions for switches with up to 2048 inputs and outputs operating under a wide variety of loads are presented. The traditional dilemma betwee n simulation model validity and its run-time where a more general purp ose model inevitably results in longer execution rimes, is eliminated by the introduction of a new parameter: the architecture of the simula tion platform. With model validity as an invariant, the simulation pla tform can range from a sequential computer via shared memory and distr ibuted memory general purpose parallel processors up to a dedicated em ulator, on the condition that the software engineering problem has bee n solved, i.e. that there is a software tool available that automates that task of generating simulation code for various platforms from a s ingle model, taking the characteristics of the platforms (granularity) into account. An analytical model of the class of applications under study gives insight into the influence of machine and problem paramete rs on simulator run-time performance, Examples of its use for the choi ce of an optimal parallel architecture for a given problem and of its use for the estimation of application behavior on a given parallel mac hine architecture are presented.