ON TIMING CONSTRAINTS OF SNOOPING IN A BUS-BASED COMA MULTIPROCESSOR

Cache only memory architecture has the potential to decrease global bu s traffic in shared-bus multiprocessors, thereby reducing the speed ga p between modern microprocessors and global backplane bus systems. How ever, the (huge) size of attraction memory (AM) in each processor node makes it difficult to properly match the access time of its state and tag storage to the bus cycle. This becomes a serious burden in effici ent snooping, much more than in conventional shared-bus multiprocessor s, especially when a high bus clock frequency is used. In this paper, we propose a scheme to relax the timing constraints of snooping in a b us-based COMA multiprocessor, which allows an efficient design of a gl obal bus protocol, and a cost-effective implementation of the overall system by using slower and cheaper memory for the state and tag storag e of AM. (C) 1998 Elsevier Science B.V.