HIERARCHICAL MOTION ESTIMATION ALGORITHMS WITH ESPECIALLY LOW HARDWARE COSTS

Digital Signal Processor (DSP) or Video Signal Processor (VSP) are bec oming popular solution for video encoding because of its flexibility c omparing with special purpose chip. The less hardware costs an algorit hm required, the better the algorithm is. Computational complexity, re quirement of on-chip memory size, amount of data fetch and times of da ta fetch are the measurements for encoding algorithms. Considering of that, a large-scale-subsample (4:1 horizontally and vertically subsamp ling) hierarchical motion estimation algorithm (LSS-HME) is proposed. It can be implemented with less hardware resources. In order to improv e estimation performance the relativity of motion vector field is expl oited. The peak signal-to-noise ratio (PSNR) degradation of reconstruc ted image is limited to about 0.1 dB compared with full search (FS) al gorithm. By using the simple motion estimation algorithm described in this paper, MPEG-2 MP@ML or even higher layers can be implemented on t he mainstream video signal processor with quite good performance.