BOTTLENECK REMOVAL ALGORITHM FOR DYNAMIC COMPACTION IN SEQUENTIAL-CIRCUITS

We present a dynamic algorithm for test sequence compaction and test a pplication time (TAT) reduction in combinational and sequential circui ts, Several dynamic test compaction algorithms for combinational circu its have been proposed, However, few dynamic methods have been reporte d in the literature for sequential circuits, Our algorithm is based on two key ideas: 1) at any point during the test generation process, we identify bottlenecks that prevent vector compaction and TAT reduction for test sequences generated thus far, and 2) future test sequences a re generated with an aim to eliminate bottlenecks of earlier generated test sequences, If all bottlenecks of a test sequence are eliminated, the sequence is dropped from the test set, Our algorithm can also tar get TAT reduction under the recently proposed partial scan-in/scan-out model by identifying and eliminating scall bottlenecks, If only the s can bottlenecks of a test sequence are eliminated, the test sequence c an be trimmed to reduce the scan-in/scan-out cycles required to apply the sequence, For sequential circuits, we propose a sliding anchor fra me technique to specify the unspecified inputs in a test sequence, The anchor frame is the first frame processed by a sequential test genera tor that is based on an iterative array model of the circuit, and the vector corresponding to the anchor frame is called the anchor vector, Under the sliding anchor frame technique, every vector in the test seq uence being extended is considered as an anchor vector, This has the s ame effect as allowing observation of fault effects at every vector in the sequence, leading to a higher quality of compaction, The final te st set generated by our algorithm cannot be further compacted using ma ny known static vector compaction or TAT reduction techniques, For exa mple, reverse or any other order of fault simulation, along with any s pecification of unspecified values in test sequences, cannot further r educe the number of vectors or TAT, Experimental results on combinatio nal and sequential benchmark circuits, and large production VLSI circu its are reported to demonstrate the effectiveness of our approach.