A METHOD FOR INCREASING THE I-DDQ TESTABILITY

At different design levels, testability is becoming more and more impo rtant since high levels of reliability are required by many applicatio ns. In this work, a novel approach to the mapping between signal lines and gate inputs is proposed, targeting the I-DDQ testability of inter nal faults, Suggesting an additional cost function for the routing pro cess, the method provides significant testability enhancements without affecting either the gate-level structure of the circuit or the inter nal layout of the gates, as proved with regards to bridging faults.