A TESTING SYSTEM FOR IMPLANTABLE CARDIOVERTER-DEFIBRILLATORS

Citation
Jm. Jenkins et al., A TESTING SYSTEM FOR IMPLANTABLE CARDIOVERTER-DEFIBRILLATORS, Journal of electrocardiology, 30, 1997, pp. 126-129
Citations number
11
Categorie Soggetti
Cardiac & Cardiovascular System
ISSN journal
00220736
Volume
30
Year of publication
1997
Supplement
S
Pages
126 - 129
Database
ISI
SICI code
0022-0736(1997)30:<126:ATSFIC>2.0.ZU;2-P
Abstract
Implantable cardioverter defibrillator (ICD) testing during the implan tation process is important in order to avoid repeated induction of ar rhythmias, which extends the implantation procedure and poses a risk t o the patient. Hence, an in vitro testing system has been designed to assist optimal device programming and avoid repetitive inductions. The system includes a high-speed computer with A/D and D/A subsystems. So ftware has been designed to eliminate repeated arrhythmia induction by real-time capture and storage of the electrogram. Subsequently, the e lectrogram can be replayed into ICD software simulators at a variety o f settings to determine candidate programming parameters. To validate the simulation system, signals were fed directly to an ICD via an atte nuator. Output event markers were captured simultaneously with the sig nal into a digital file to assess the device performance. Four ventric ular tachycardia (VT), three supraventricular tachycardia, (SVT), thre e atrial flutter (AFL), three atrial fibrillation (AF), anti ten ventr icular fibrillation (VF) passages were used to verify the system. Test settings were 110-160 beats/min for detection rate and 5 seconds for shock delay. The simulator and ICD detected the episodes for all passa ges at the 110 beats/min setting. For the setting of 160 beats/mir, tw o VTs, two SVTs, three AFLs, and nine VFs were detected by the device, but no Afb triggered a shock. The simulator detection criteria were m et by two VTs, two SVTs, three AFLs, ten VFs, and one AE. The mean det ection time was 6,869-7,330 ms (110-160 beats/min) for the simulator a nd 7,840-8,170 ms for device. Comparison of results showed general agr eement between simulator and device. Results demonstrated that device behavior at a variety of settings can he elucidated by the simulator f or selection of optimal performance. The automated system can also fun ction as a test bed for evaluation of new algorithms during device dev elopment and design.