REDUCING THE MEAN LATENCY OF FLOATING-POINT ADDITION

Addition is the most frequent floating-point operation in modem microp rocessors. Due to its complex shift-add-shift-round data flow, floatin g-point addition can have a long latency. To achieve maximum system pe rformance, it is necessary to design the floating-point adder to have minimum latency, while still providing maximum throughput. This paper proposes a new floating-point addition algorithm which exploits the ab ility of dynamically scheduled processors to utilize functional units which complete in variable time. By recognizing that certain operand c ombinations do not require all of the steps in the complex addition da ta flow, the mean latency is reduced. Simulation on SPECfp92 applicati ons demonstrates that a speedup in mean addition latency of 1.33 can b e achieved using this algorithm, while maintaining single-cycle throug hput. (C) 1998 Published by Elsevier Science B.V. All rights reserved.