A DATA-INTERLACING ARCHITECTURE WITH 2-DIMENSIONAL DATA-REUSE FOR FULL-SEARCH BLOCK-MATCHING ALGORITHM

Authors
LAI YK CHEN LG
Citation
Yk. Lai et Lg. Chen, A DATA-INTERLACING ARCHITECTURE WITH 2-DIMENSIONAL DATA-REUSE FOR FULL-SEARCH BLOCK-MATCHING ALGORITHM, IEEE transactions on circuits and systems for video technology, 8(2), 1998, pp. 124-127
Citations number
6
Categorie Soggetti
Engineering, Eletrical & Electronic
Journal title
IEEE transactions on circuits and systems for video technology → ACNP
ISSN journal
10518215
Volume
8
Issue
2
Year of publication
1998
Pages
124 - 127
Database
ISI
SICI code
1051-8215(1998)8:2<124:ADAW2D>2.0.ZU;2-D
Abstract
This paper describes a data-interlacing architecture with two-dimensio nal (2-D) data-reuse fur fun-search block-matching algorithm, Based on a one-dimensional processing element (PE) array and two data-interlac ing shift-register arrays, the proposed architecture can efficiently r euse data to decrease external memory accesses and save the pin counts , It also achieves 100% hardware utilization and a high throughput rat e, In addition, the same chips can Pre cascaded for different block si zes, search ranges, and pixel rates.