VERTICAL MOSFET WITH BURIED GATE

The authors are investigating an SPE method, using the low-pressure ch emical vapor deposition (LPCVD) system, that is utilized in ordinary S i LSI processes. A vertical MOSFET with a unique structure was devised by applying this method. The device assumes a vertical power MOSFET a nd features in the buried gate. By driving the buried gate in parallel with the ordinary gate, the drain current is increased. This is due t o two effects. First, the effect of the channel formed by the buried g ate. Second, the effect of the storage layer formed in the low-density n region below the buried gate, which attracts the drain current unif ormly. A lateral SOI MOSFET is constructed and is evaluated on the sam e Si substrate as the vertical MOSFET The purpose is to evaluate the c ircuit elements for an intelligent power MOS. The MOS operation is ver ified for both nMOS and pMOS. The off-state leak current is less than 2 x 10(-12) A. (C) 1998 Scripta Technica.