STUDIES ON REDUCING LEAKAGE CURRENT OF LARGE-AREA SILICON MICROSTRIP SENSORS

8 x 4 cm(2) single-sided p(+) -i (or nu)-n(+) silicon microstrip senso rs with coupling capacitors and polysilicon bias resistors were fabric ated with the planar technology, and various techniques used to reduce the leakage currents of sensors and their results are presented. Diff erent gettering processes have been employed to remove the impurities and defects from the sensor active regions, and the Electronic Researc h and Service Organization (ERSO's) Charge-Coupled Device (CCD) getter ing technique, combined with backside polysilicon and oxide-nitride-ox ide (ONO) deposition process, was found to be the most effective and s uitable one. From the measurement results of the special p(+) -i (or n u)-n(+) junction test structures, it was found that the sensor leakage current mainly came from the side-wall leakage of its p(+)-strip. A m odified LOCal Oxidation of Silicon (LOCOS) isolation process has been used to reduce this side-wall leakage. Also, the Sirtl-etch analysis o f the sensor revealed that the side-wall leakage current has been caus ed by residual boron-implantation defects after annealing. These defec ts would concentrate along the edge of p(+)-strip and be enhanced to c ause dislocations by the film-edge-induced stress effect. Several anne aling techniques have also been studied to remove the boron-implantati on damages. The fabricated prototype sensors have been tested in a bea m at the CERN Super Proton Synchrotron area. The test results showed t hat the sensor concept under study is feasible.