Reduced surface field lateral double-diffused MOS transistors for the
driving circuits of plasma display panel and field emission display in
the 120 V region have been integrated for the first time into a low-v
oltage 1.2 mu m analog CMOS process using p-type bulk silicon. This me
thod of integration provides an excellent way of achieving both high p
ower and low voltage functions on the same chip; it reduces the number
of mask layers and also the cost of fabrication. The lateral double-d
iffused MOS transistor with a drift length of 6.0 mu m and a breakdown
voltage greater than 150 V was self-isolated to the low voltage CMOS
ICs. The measured specific on-resistance of the lateral double-diffuse
d MOS is 4.8 m Omega.cm(2) at a gate voltage of 5 V.