S. Tongsima et al., REDUCING DATA HAZARDS ON MULTI-PIPELINED DSP ARCHITECTURE WITH LOOP SCHEDULING, Journal of VLSI signal processing systems for signal, image, and video technology, 18(2), 1998, pp. 111-123
Citations number
16
Categorie Soggetti
Computer Science Information Systems","Engineering, Eletrical & Electronic","Computer Science Information Systems
Computation intensive DSP applications usually require parallel/pipeli
ned processors in order to meet specific timing requirements. Data haz
ards are a major obstacle against the high performance of pipelined sy
stems. This paper presents a novel efficient loop scheduling algorithm
that reduces data hazards for such DSP applications. This algorithm h
as been embedded in a tool, called SHARP, which schedules a pipelined
data flow graph to multiple pipelined units while hiding the underlyin
g data hazards and minimizing the execution time. This paper reports s
ignificant improvement for some well-known benchmarks showing the effi
ciency of the scheduling algorithm and the flexibility of the simulati
on tool.