C. Basaran et al., THERMOMECHANICAL FINITE-ELEMENT ANALYSIS OF PROBLEMS IN ELECTRONIC PACKAGING USING THE DISTURBED STATE CONCEPT - PART 2 - VERIFICATION AND APPLICATION, Journal of electronic packaging, 120(1), 1998, pp. 48-53
The finite element procedure with the unified disturbed state modellin
g concept presented in Part I, Basaran et al. (1998), is verified here
with respect to laboratory test results for Pb40/Sn60 eutectic solder
alloy. This solder alloy is a commonly used interconnection material
for surface mount technology packages. It is demonstrated that the pro
posed procedure provides highly satisfactory correlation with the obse
rved laboratory behavior of materials and with test results for a chip
-substrate system simulated in the laboratory.