HIGH-THROUGHPUT BLOCK-MATCHING VLSI ARCHITECTURE WITH LOW MEMORY BANDWIDTH

A full-search block-matching architecture which features high throughp ut, low data input lines I and low memory bandwidth is proposed. It re duces memory I/O requirements by the maximum reuse of search data usin g on-chip memory. It also promises a high throughput rate by the conti nuous calculation of all block distortions in a search area using two search data input hows without processing any invalid block distortion , and by the continuous process of the neighbored reference blocks rem oving the initialization period between blocks. The processor for -16/ +15 search ranges, implemented in the total 220k gates using 0.6 mu m triple-metal CMOS technology, can operate at a 66 MHz clock rate, and therefore is capable of encoding H.263(4CIF), MPEG2(MP@ML), and other multimedia applications.