CLOCK-CONTROLLED NEURON-MOS LOGIC GATES

A new clock-controlled circuit scheme has been introduced in the basic architecture of neuron-MOS (neuMOS or vMOS) logic gates. In this sche me, the charge on a neuMOS Boating gate is periodically refreshed by a clock-controlled switch. A special refreshing scheme in which fluctua tions in device parameters are automatically canceled has been employe d. As a result, the number of multiple logic levels that can be handle d in a neuMOS floating gate has been increased. In addition, the data subtraction operation directly conducted on the floating gate has beco me possible. All of these circuit techniques have enhanced the functio nality of a neuMOS logic gate a great deal. In order to achieve a low power operation, latched-sense-amplifier circuitries are also introduc ed for logic decision. Test circuits were fabricated in a double-polys ilicon CMOS process, and the basic circuit operations are demonstrated .