NOVEL SELF-ALIGNED TI SILICIDE PROCESS FOR SCALED CMOS TECHNOLOGIES WITH LOW SHEET RESISTANCE AT 0.06-MU-M GATE LENGTHS

A novel Ti self-aligned silicide (salicide) process using a combinatio n of low dose Molybdenum and preamorphization (PAI) implants and a sin gle rapid-thermal-processing (RTP) step is presented, and shown to be the first Ti salicide process to achieve low sheet resistance at ultra short 0.06-mu m gate lengths (Mean = 5.2 Omega/sq, Max = 5.7 Omega/sq at 0.07 mu m; Mean = 6.7 Omega/sq, Max = 8.1 Omega/sq at 0.06 mu m, Ti Si2 thickness on S/D = 38 nm), in contrast with previous Ti salicide p rocesses which failed below 0.10 mu m. The process was successfully im plemented into a 1.5 V, 0.12-mu m CMOS technology achieving excellent drive currents (723 and 312 mu A/mu m at I-OFF = 1 nA/mu m for nMOS an d pMOS, respectively).