A THRESHOLD LOGIC GATE BASED ON CLOCKED COUPLED INVERTERS

Authors
RAMOS JF LOPEZ JAH MARTIN MJ TEJERO JC GAGO A
Citation
Jf. Ramos et al., A THRESHOLD LOGIC GATE BASED ON CLOCKED COUPLED INVERTERS, International journal of electronics, 84(4), 1998, pp. 371-382
Citations number
11
Categorie Soggetti
Engineering, Eletrical & Electronic
Journal title
International journal of electronics → ACNP
ISSN journal
00207217
Volume
84
Issue
4
Year of publication
1998
Pages
371 - 382
Database
ISI
SICI code
0020-7217(1998)84:4<371:ATLGBO>2.0.ZU;2-X
Abstract
In this paper we present both a new design for a threshold logic gate, based on clocked cross-coupled inverters, and the way to optimize the implementation of threshold functions using this gate. The main chara cteristics of the threshold gate are low power consumption tit does no t consume static power) and high speed.