SCALP - AN ITERATIVE-IMPROVEMENT-BASED LOW-POWER DATA-PATH SYNTHESIS SYSTEM

In this paper, we present SCALP, a comprehensive low-power data path s ynthesis system that performs the various high-level synthesis tasks ( transformations, scheduling, clock selection, module selection, and ha rdware allocation and assignment) with an aim of reducing the power co nsumption in the synthesized data path. Focusing on only one or a smal l subset of the high-level synthesis tasks makes it difficult to reali ze the full potential for power savings at the algorithm and architect ure levels, Our synthesis algorithms, which are based on an interative improvement strategy with efficient pruning techniques, are capable o f performing the various high-level synthesis tasks (and considering t heir interactions) in an efficient manner. Supply voltage and clock pe riod pruning strategies are used for quickly eliminating inferior desi gn points during the search for the minimum power solution. Estimating switched capacitance accurately at intermediate stages during high-le vel synthesis can be challenging since the exact structure of the circ uit, which affects both physical capacitance and switching activity, m ay not be available, and due to the high computational complexity of r unning register-transfer level power analysis tools several times duri ng high-level synthesis. SCALP overcomes the above problems by maintai ning a complete image of the structural register-transfer level (RTL) circuit (this is possible since we have a complete solution at any poi nt during iterative improvement), and employing a very fast switched c apacitance estimation technique that is based on the concept of switch ed capacitance matrices, Our system fan handle diverse module librarie s and utilize complex scheduling constructs such as multicycling, chai ning, and structural pipelining, Retiming and functional pipelining ar e used in our system to meet tight performance constraints, and to ena ble the ensuing synthesis steps to better explore the implementation s pace, Results on several real-life examples are presented to demonstra te the effectiveness of the algorithm, Power estimates obtained using switch-level simulation after layout indicate that up to an order-of-m agnitude of power savings can he obtained using our synthesis system.