TIGER - AN EFFICIENT TIMING-DRIVEN GLOBAL ROUTER FOR GATE ARRAY AND STANDARD CELL LAYOUT DESIGN

In this paper, we propose an efficient timing-driven global router, TI GER, for gate array and standard cell layout design. Unlike other conv entional global routing techniques, interconnection delays are modeled and included during the routing and rerouting process in order to min imize the maximum channel density for gate arrays or the total track n umber for standard cells, as well as to satisfy the timing constraints in TIGER. The timing-driven global routing problem is formulated as a multiterminal, multicommodity network flow problem with integer flows under additional timing constraints, Two novel performance-driven Ste iner tree algorithms are proposed to generate the initial global routi ng trees. A critical-path-based timing analysis method is used to guar antee the satisfaction of timing constraints. Experimental results bas ed on MCNC (ISCAS) benchmarks show that TIGER can obtain better result s than or comparable results with TimberWolf 5.6.