DELAY-TIME SENSITIVITY ANALYSIS OF MULTIGENERATION BICMOS DIGITAL CIRCUITS

The speed sensitivity of BiCMOS circuits to changes in the key MOS/BJT device parameters is analysed. The study takes into account the chang es in the forward transit time, the knee current, the collector resist ance, the base resistance, and the current gain of the bipolar transis tor and the channel length and width, threshold voltage, and oxide thi ckness of the MOS transistor. The relationships between the key proces s parameters and the overall speed sensitivity are reported. The analy sis also covers the effects of the output load capacitance, scaling th e technology, and the quality of the bipolar device on the delay sensi tivity. Sensitivity coefficients are defined and generated for the con ventional BiCMOS circuit as well as two recently reported circuits des igned for low-voltage operation. A method to calculate the worst case speed degradation for a given set of device and process parameters' to lerances is described. HSPICE is used to generate the numerical result s for the three technologies (5 V, 0.8 mu m), (3.3 V, 0.5 mu m), and ( 2.2 V, 0.2 mu m).