CONFIGURABLE MULTIPLIER BLOCKS FOR EMBEDDING IN FPGAS

A new architecture for configurable blocks is proposed which can be us ed to construct multipliers. An array of these blocks is capable of be ing configured to perform any 4m bit x 4n bit signed/unsigned binary m ultiplication. The blocks are designed to be embedded within a convent ional FPGA structure to increase the functionality of the device by fr eeing valuable general reconfigurable resources, particularly when use d in the area of image processing.