LOW-POWER AND LOW-VOLTAGE D-LATCH

Authors
CHING LP LING OG
Citation
Lp. Ching et Og. Ling, LOW-POWER AND LOW-VOLTAGE D-LATCH, Electronics Letters, 34(7), 1998, pp. 641-642
Citations number
3
Categorie Soggetti
Engineering, Eletrical & Electronic
Journal title
Electronics Letters → ACNP
ISSN journal
00135194
Volume
34
Issue
7
Year of publication
1998
Pages
641 - 642
Database
ISI
SICI code
0013-5194(1998)34:7<641:LALD>2.0.ZU;2-J
Abstract
A novel low-power and low-voltage static D-latch is presented using we ak transistors where the driving capability is not crucial. Based on t he HSPICE simulation with 0.8 mu m technology file from IME. power con sumption has been reduced by 11% to 34%. The lowest operating voltage is 1.6V.