400-MHZ RANDOM COLUMN OPERATING SDRAM TECHNIQUES WITH SELF-SKEW COMPENSATION

High-speed data transfer is a key factor in future main memory systems . DDR SDRAM (double-data-rate synchronous-DRAM) is one of the candidat es for high-speed memory. In this paper we present three techniques to achieve a short access time and high data transfer rate for DDR-SDRAM 's. First, a self-skew compensating technique enables 400-Mbit/s addre ss and data detection, Second, a novel trihierarchical WL scheme reali zes multibank operation without access or area penalties, Third, an in terleaved array access path doubles the array operating frequency and it enables 400-MHz random column operation. A 16-bank 256-Mbit DDR SDR AM circuit has been designed, and the possibility of the realization o f random column 200 MHz x 32 DDR operation, namely, 1.6-Gbyte/s data r ate operation, has been confirmed.