BIPARTITION AND SYNTHESIS IN LOW-POWER PIPELINED CIRCUITS

By treating each different output pattern as a state, we propose a low power architecture for pipelined circuits using bipartition. It is po ssible that the output of a pipelined circuit transit mainly among som e of different stares. If some few stales dominate most of the time, w e could partition the combinational portion of a pipelined circuit int o two blocks: one that contains the few states with high activity is s mall and the other that contains the remainder with low activity is bi g. The original pipelined circuit is bipartitioned into two individual pipelined circuits. An additional combination logic block is introduc ed to control which of the two partitioned blocks to work. Power reduc tion is based on the observation that most time the small block is at work and the big one is at idle. In order to minimize the power consum ption of this architecture, we present an algorithm that can improve t he efficiency of this additional control block. Experiments with MCNC benchmarks show high percentage of power saving by using our new archi tecture for low power pipelined circuit design.