AN EFFECTIVE ROUTING METHODOLOGY FOR GB S LSIS USING DEEP-SUBMICRON TECHNOLOGY/

This paper presents a routing methodology and a routing algorithm used in designing Gb/s LSIs with deep-submicron technology. A routing meth od for controlling wire width and spacing is adopted For net groups cl assified according to wire length and maximum-allowable-delay constrai nts. A high-performance router using this method has been developed an d can handle variable wire widths, variable spacing, wire shape contro l, and low-delay routing. For multiterminal net routing, a modificatio n of variable-cost maze routing (GVMR) is effective for reducing wire capacitance (net length) and decreasing net delay. The methodology des cribed here has been used to design an ATM-switch LSI using 0.25-mu m CMOS/SIMOX technology. The LSI has a throughput of 40 Gb/s (2.5 Gbps/p in) and an internal clock frequency of 312 MHz.