APPLICATION OF CIRCUIT-LEVEL HOT-CARRIER RELIABILITY SIMULATION TO MEMORY DESIGN

We have applied hot-carrier circuit-level simulation to memory periphe ral circuits of a few thousand to over 12K transistors using a simple but accurate degradation model for reliability verification of actual memory products. By applying simulation to entire circuits, it was fou nd that the location of maximum degradation depended greatly upon circ uit configuration and device technology. A design curve has been devel oped to quickly relate device-level DC lifetime to circuit-level perfo rmance lifetime. Using these results in conjunction with a methodology that has been developed to predict hot-carrier degradation early in t he design cycle before TEG fabrication, accurate total-circuit simulat ion is applied early in the design process, making reliability simulat ion a crucial design tool rather than a verification tool as technolog y advances into the deep sub-micron high clock rate regime.