MULTIPLIER-FREE IIR FILTER REALIZATIONS WITH PERIODICALLY TIME-VARYING COEFFICIENTS

In this paper, the periodically time-varying (PTV) structure, previous ly proposed for realizing FIR filters, is extended to IIR filter reali zation. The realization consists of ternary ({0, +/-1}) or quinary ({0 , +/-1, +/-2}) PTV coefficients with simple input and output units. Co efficient multiplications as well as the input and output units requir e no hardware multiplier, which helps increase the processing speed or reduce the chip area. Bit-level architectures are presented. The regu larity and local interconnection of the architectures help simplify VL SI design and layout.