A LOW-POWER RECEIVER ARCHITECTURE FOR 4 MBPS INFRARED WIRELESS COMMUNICATION

A high performance and low power architecture is devised for a 4 Mbps infrared wireless communication system dedicated to mobile computing. In this architecture, 4PPM (4-Pulse Position Modulation) infrared sign als detected by an infrared receiver are digitized into TTL interface level pulses, and the digitized pulses are demodulated by a I-bit digi tal demodulator. To extend the range of the link length, a 4PPM demodu lator is synthesized to implement a demodulation algorithm which is co nstructed so as to accommodate the output tolerance of the infrared re ceiver. A part of the experimental results shows that the proposed 4 M bps infrared communication system can achieve an error free link in th e range of 0-140 cm at power consumption of 245 mW and 65 mW for trans mitting and receiving, respectively. The communication controller is i ntegrated in a 0.6 mu m CMOS standard-cell chip which contains 10,015 transistors on a 12 mm(2) die.