USING MODEL-CHECKING FOR TIMED AUTOMATA TO PARAMETERIZE LOGIC CONTROLPROGRAMS

Authors
KOWALEWSKI S ENGELL S HUUCK R LAKHNECH Y LUKOSCHUS B URBINA L
Citation
S. Kowalewski et al., USING MODEL-CHECKING FOR TIMED AUTOMATA TO PARAMETERIZE LOGIC CONTROLPROGRAMS, Computers & chemical engineering, 22, 1998, pp. 875-878
Citations number
8
Categorie Soggetti
Computer Science Interdisciplinary Applications","Engineering, Chemical","Computer Science Interdisciplinary Applications
Journal title
Computers & chemical engineering → ACNP
ISSN journal
00981354
Volume
22
Year of publication
1998
Supplement
S
Pages
875 - 878
Database
ISI
SICI code
0098-1354(1998)22:<875:UMFTAT>2.0.ZU;2-Q
Abstract
In this contribution we describe how the modeling and analysis framewo rk of Timed Automata can be used to determine valid parameter ranges f or timers in logic control programs. The procedure is illustrated by m eans of a simple process engineering example for which the complete Ti med Automata model is presented. To analyse the model, the tool HyTech is used which provides routines to determine values of model paramete rs depending on. reachability conditions. (C) 1998 Elsevier Science Lt d. All rights reserved.