OPTIMIZED BIT-SERIAL MODULAR MULTIPLIER FOR IMPLEMENTATION ON FIELD-PROGRAMMABLE GATE ARRAYS

A high-speed architecture for bit serial modular multiplication is pre sented. The design of this array is highly regular, allowing the speci fic logic and routing resources available in field programmable gate a rrays (FPGAs) to be exploited. Furthermore, an optimised array is pres ented which exploits the reprogrammability of the FPGA, such that a lo nger bit length can be implemented on the same FPGA.