PASS-TRANSISTOR ADIABATIC LOGIC WITH NMOS PULL-DOWN CONFIGURATION

A new low power adiabatic logic family, pass-transistor adiabatic logi c with NMOS pull-down configuration, is presented. For a 2:1 multiplex er, a power saving of similar to 80% is achieved, compared to a 2N-2N2 P logic circuit at 20 MHz. Compared to pass-transistor adiabatic logic using single power-clock supply (PAL), the 'tri-state' problem is sol ved, while power consumption is comparable. A four phase sinusoidal cl ock power supply is employed in the new logic family, which facilitate s pipelining hence leading to higher throughput, compared to PAL.